MOS devices, particularly MOS transistors, make up a large part of most high-density integrated circuit devices. Such devices are characterized by a thin layer of silicon oxide over a portion of a monocrystalline silicon substrate over which lies a gate electrode, usually of polycrystalline silicon, to which is applied a voltage for affecting in a desired manner the properties of the underlying silicon.
For reliable operation, it is important that the integrity of the gate oxide be maintained. However, gate-oxide pinholes have long been one of the most serios problems facing MOS devices. Moreover, as MOS technology advances, and the density of MOS devices in an integrated circuit are increased, it becomes necessary to employ very thin oxides, sometimes only a few monolayers thick. Because of the importance of compatibility with existing circuits, it is usual to operate such thin oxide devices at the standard five volt power supply which imposes a very high electric field across the oxide. Use of such high electric fields makes it imperative that the oxide be free of defects, if the integrated circuit is to operate reliably in the field.
Defective devices once incorporated into equipment are very hard to find and expensive to replace, particularly if the equipment is in field use. Accordingly, there is considerable interest in methods to screen devices having defective oxides prior to their incorporation into equipment.
The most common method for screening oxides is burn-in. This typically involves operating a device at a higher than normal voltage level for a prescribed period of time, sometimes at elevated temperatures. Oxide failures tend to be greatly accelerated by higher voltages, and to a lesser extent by higher temperatures.
However, it is important that the applied voltage be less than the gate punch-through voltage, which is apt to be only slightly larger than the maximum power supply voltage in state-of-the-art devices. This imposes limits on the magnitude of the power supply voltage that can be safely employed without introducing hot electron problems or causing transistor shorts.
Another factor that is important is the need to stress essentially equally all of the gate oxides in an integrated circuit device. This becomes difficult in complex devices, such as random logic devices. In such complex devices, it is difficult to find a set of input states that will stress all of the internal transistors essentially equally. As a result, burn-in is becoming of less utility in screening gate oxides.
Another common method of screening gate oxides is to apply a short high voltage stress to the oxides during a final test of the device. This technique has been most successfully applied for testing the oxide layer of the MOS capacitors used in dynamic random access memories (DRAMs). This has worked well in this application because all the capacitor plates are tied to a common node. However, this technique is very difficult to apply to random logic devices because it requires a set of test vectors that stress each gate once and only once. Alternately, it would be required to add additional circuitry to allow all gates to be connected to one or a few nodes, which wold undesirably add to the number of devices in the integrated circuit. For these reasons, this screening technique has not been applied to any significant extent to random logic devices.
There is the additional problem that as the wear out lifetime of the oxides approaches the expected lifetime of the device, the stress used to weed out potentially defective oxide layers may reduce the remaining lifetime of the good oxide layers.
To avoid these problems, non-destructive gate oxide screening techniques were developed. Such techniques look for very low levels of leakage through the oxide without requiring the need for high voltages to stress the oxide layers. This approach is based on the theory that a defective oxide will show a higher FowlerNordheim tunneling current even at low voltages. In this technique, a voltage is placed across the oxide layer being tested of a magnitude that provides a level of Fowler-Nordheim tunneling current that is just below the detectable level of a good oxide layer. As a result, a defective oxide layer will yield a detectable current while a good one will not and will not be degraded.
While this technique is readily applicable to DRAMs it cannot be readily applied to random logic devices because it is not possible to sense very small currents if the current path includes a pass transistor. Thus the gate electrode of the oxide layer being tested would require a direct low resistance path to an external sense device or to an on-chip test structure to detect the low level of current. This generally is not practicable.